1. Field of the Invention
The present invention relates to a data circuit-terminating equipment for terminating a data transmission line.
The invention is particularly concerned with a data circuit-terminating equipment for connecting various asynchronous data terminal equipments with a PCM transmission line.
2. Description of the Prior Art
The prior art relating to a conventional data circuit-terminating equipment for various synchronous data terminal equipments is disclosed in U.S. Pat. No. 4,694,470 which will be described.
With reference to FIGS. 1 and 2, the principle of the prior art will first be described in detail.
FIG. 1 is a diagram showing the principles established to accommodate a terminal equipment having a speed of 19.2 Kbps in an electronic exchange with a 64 Kbps transmission line. Flag synchronizing bits (F bits) at a bit "0" position of a frame "O" is to notify the frame position to a receiving party by transmitting a flag pattern "1010". The receiving party can easily recognize the frame position by detecting the flag pattern. To accommodate the 19.2 Kbps terminal equipment in the 64 Kbps transmission line, it is necessary only to accommodate data D0 to D23 of 24 bits in specified bit positions every 10 multi frames, as shown in FIG. 1. Incidentally, blank fields are not used.
FIG. 2 shows the principles established to accommodate a 9.6 Kbps terminal equipment. If data D0 to D11 of 12 bits which is one-half that in the case of 19.2 Kbps in FIG. 1 can be accommodated, a transmission speed conversion is possible. In this instance, however, in order to accommodate data of different transmission speeds in the same circuit, the same data is inserted twice in succession, as depicted in FIG. 2, thereby to accommodate data of a transmission speed different from 19.2 Kbps. In a similar manner, data of 4.8 Kbps and data of 2.4 Kbps can be accommodated by inserting the same data four times and eight times in succession, respectively.
A description will be given, with reference to FIG. 3, of the principle of a synchronization establishing bit (a SY bit) at the bit 0 position of the frame 1. In FIG. 3, reference characters L.sub.1 and L.sub.2 indicate lines which are transmitting and receiving lines, respectively, as viewed from the party of equipment (A), but receiving and transmitting lines, as viewed from the party of equipment (B). The following description will be given, with the above lines as viewed from the party (A).
The line interface equipment (data circuit-terminating equipment) DCEa on the party (A) detects the F bit on the receiving line L.sub.2 and, upon establishment of synchronization, puts the SY bit into its ON state and provides it on the transmitting line L.sub.1. The equipment DCEb on the party (B) similarly provides the ON state of the SY bit on the receiving line L.sub.2 when synchronization of the transmitting line L.sub.1 is established by the F bit. Thus the equipment DCEa on the party (A) can detect the synchronized state of the transmitting line L.sub.1 by monitoring the SY bit on the receiving line L.sub.2. This is also true for the equipment DCEb on the party (B). Control line information defined by JIS-C6361 is accommodated in bits 7 of frames 0 to 3. In FIGS. 1 and 2, signals above oblique lines are control signals to be provided on the transmitting line L.sub.1 and signals below the oblique lines are control signals to be received from the receiving line L.sub.2.
In FIG. 2, RS indicates a request-to-send signal for requesting transmission, CD a carrier detect signal, CS and CS' clear-to-send signals, ER an equipment ready signal, DR a data set ready signal and CI' call indicator signal.
Each equipment DTEa and DTEb includes an address sending circuit respectively to send out an address. A modem MDM has an address receiving circuit which receives an address and sends out a defined signal to a line or an equipment connected with the modem MDM in which the line or the equipment is not shown in FIG. 3. The address is received or transmitted between the address sending and receiving circuits.
FIG. 4 shows a method for accommodating control signals between terminal equipments, and FIGS. 5A and 5B a method for accommodating control signals between a terminal equipment and a modem.
In FIG. 4, since terminal equipments (A) and (B) are interfaces of the same input/output relationship, sending data SD sent from the terminal equipment (A) is received as receiving data RD at the terminal equipment (B). Likewise, the other lines are connected as shown. Transmission lines are shown to be connected to have a one-to-one correspondence to each other for the sake of clarity, but since data is accommodated in such formats as depicted in FIGS. 1 and 2, the transmission lines are concentrated to the two transmitting and receiving lines L.sub.1 and L.sub.2, as shown in FIG. 3. As is evident from the principles described previously in conjunction with FIGS. 1 and 2, since the control signals are sampled only once every 10 frames, for example, even if the terminal equipment (A) turns ON the RS (request-to-send) signal, the carrier detect signal CD in the terminal equipment (B) is delayed by 1.25 ms at most in turning ON. Accordingly, the terminal equipment (B) cannot receive the receiving data RD from the terminal equipment (A) if it arrives before the carrier detect signal CD turns ON.
To avoid this, the carrier detect signal CD is held in the on state during data reception, by determining the value of the request-to-send signal in terms of the logic OR of its previous and current sampled values and by determining the state of data transmission over the transmission line, as shown below in Table 1.
TABLE 1 ______________________________________ Previous state Current state Transmission state ______________________________________ OFF OFF OFF OFF ON ON ON OFF ON ON ON ON ______________________________________
FIG. 6 shows the relationship between the request-to-send signal RS and the send data SD. The request-to-send signal RS and the data SD bear such a relation that data D is valid while the request-to-send signal RS is in the ON state. Sampling it in units of 10 multi frames (1.25 ms), RS sample pulses (RSP) are obtained. However, by delaying the data D by 1.25 ms and providing it as the send data SD on the transmission line and making the state decision of Table 1 to determine the value of the request-to-send signal RS, the relationship between the request-to-send signal RS and the data D becomes as shown, assuring the above-said relationship.
The delay of data for 1.25 ms can be accomplished by providing 24-stage (24-BIT) registers, as shown in FIG. 7, and by selecting timings, load pulses to be 1.25 ms for shifting the data from the register REGa to the register REGb. The reason for the provision of 24 stages of registers is to insert 24 bits in the afore-mentioned 10 multi frames.
FIG. 5A shows the connection of a terminal equipment and a modem. FIG. 5B shows a time chart illustrating signals 7 at various portions of FIG. 5A. Unlike in FIG. 4, the send data SD is connected to the sending data SD of the modem in a manner to have a one-to-one correspondence to each other. The other control signals are also connected to have a one-to-one correspondence to each other, as shown. Furthermore, the signals SC and CI, which are output from the modem, can easily be implemented by the connection to CS' and CI'.
A calling sequence between a terminal equipment (A) and a modem will be described refering to FIG. 5B.
When the terminal equipment (A) calls, the equipment ready signal ER of (a) and the request-to-send signal RS of (b) are turned from "0s" to "1s" to be transmitted to the modem. Receiving the signals ER and RS, the modem confirms that a data terminal equipment connected to the modem by a line can receive signals from the data terminal equipment (A) by checking the state of the line. Then the modem turns on a clear-to-send signal CS' from a "0" to a "1" as shown in (c). The SY bit has shown a "1" and so the clear-to-send signal CS of (d) is turned on from a "0" to a "1".
Receiving the CS signal of a "1", the data terminal equipment (A) sends out the sending data SD of (e). An address is transmitted as the first data of the sending data SD.
The line interface equipments (data circuit-terminating equipments) shown in FIGS. 3, 4 and 5A transmits data from a synchronous data terminal equipment and various control signals to a transmission line by multframe as shown in FIGS. 1 or 2 at a fixed rate of 64 kilobits per second.
On the other hand, various data terminal equipments have been available recently. Some of those data terminal equipments operate by their own clock independently of the timing of the transmission line. There has accordingly been a great increase in the demand to asynchronously transmit data from asynchronous data terminal equipments on the PCM transmission line. However, there is a problem that such an asynchronous data terminal equipment can not be connected with the PCM transmission line having various transmission rates.
There is another problem to be solved. The recommendations of the V25 bis of CCITT was enforced in 1984. The line interface equipments (data circuit-terminating equipments) as shown in FIGS. 4 and 5A can not transmit an address as one of data to be transmitted to satisfy the recommendations. Referring to FIG. 5A, such a problem will be described.
It is defined in the recommendations of the V25 bis of CCITT that the clear-to-send signal CS must be turned from a "0" to a "1" in spite of the state of the request-to-send signal RS when the clear-to-send signal CS' becomes from a "0" to a "1". And it is further defined that the request-to-send signal RS being a "1" is not needed when the equipment ready signal ER is transmitted. The data terminal equipment (A) must therefore turn the request-to-send signal RS from a "0" to a "1" after receiving the clear-to-send signal CS turned to a "1".
In FIG. 5A, an AND gate in the line interface equipment (A) can however not send out the clear-to-send signal CS of a "1" in spite of "1s" of the SY bit and the clear-to-send signal CS' when the request-to-send signal RS shows a "0" and so the clear-to-send signal CS of a "0" is received by the data terminal equipment (A) which can not turn the request-to-send signal RS from a "0" to a "1". Therefore the communication can not be started.